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Curriculum
Vitae'
About Me
Graduated from India with a Bachelor of Engineering(equiv. BS in US) in Electronics
and Communications, i have always had an acute inclination towards system programming.
All of my career i have worked in various levels of system programming including, developing
from scratch a minimal RTOS for MIPS, Device Drivers for Windows, Assembly for post and pre
silicon verification on MIPS based SOCs, and more.
With all these days of system programming, i am now working on a material titled "Real time
Programming - a Pessimistic Approach", which explains how and what to do when a real time
system faults, and how to prevent faulting of realtime systems at the design and programming
level.
Staying in this domain of system programming i have been staying close with C and assembly
language programming all the time. I have also had a chance to work closely with various processor
architectures some of which i worked intensively like the MIPS Platforms.
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Personal
Details
Residential:
450, N.Mathilda Ave,
#F108, Sunnyvalle,
CA - 94085,
Phone:
408-732-6132
Sex:
Male.
Nationality:
Indian.
Age: 23.
Email: karthiksamynathan@yahoo.com
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Experience
Summary
Nvidia Corporation
System Software Engineer
July 2002 Till Present
Okay, so this is where i am. In the Bay Area - Silicon Valey. I currently work
for Nvidia Corporation in their Mobile Group, we work for a team which aims at
developing the lowest level of resource management modules for Nvidia's high
performance low power Mobile GPU's. Nvidia is a nice place to work, because of
the competitive environment that is maintained inside.
Atheros Communications Incorporated
Design Engineer
October 2001 to July2002
Atheros CommunicationsInc. Is a company
creating Wireless LAN chipsets (802.11x Combo). I started at
Atheros on development of low-level functionality to bring up
and do post silicon DV of the MIPS 4kp Core, including Cache
initialization, Structured Interrupt handling, Prioritization
of interrupts and more. These low level routines were developed
with C and assembly. Have also a good experience on 802.11a
devices, operation and software design. I have very closely worked
with the MIPS platform for the entire of my career (more than a
year and half).
The next assignment was to drive a small team to develop a
microkernal RTOS with minimal configurations to bring up test boards
and run tests on them. Previously tests were run sequentially and
the stress on the bus was not a typical real time example, but
after we would complete this RTOS we would be able to simulate a
real time environment by running simultaneous tests and putting
lots of traffic on the system bus. The targeted platforms were
MIPS based SOC solutions.
Occasionally I also work with the Digital verification team to
develop and deploy assembly language tests on the MIPS RTL model
for their simulation tests, this has provided me an insight into
VERA and Verilog. In general I could move quickly across the
hardware software boundary.
I also had a chance to work on NDIS drivers for our client cards,
and an all Atheros kernel driver.I have good understanding of windows
internals and driver architectures and implementation specifics,
Cisco ODC - HCL India Branch
Member o Technical Staff
July 2000 till October 2001
Previous to Atheros I was working at the Cisco offshore development
center Chennai, India, which is run by HCL Technologies Ltd,
an Indian base software company. I worked in the ‘IOS Classic
infrastructure Group’, where we were responsible to sustain
and do feature developments on the IOS which is Cisco's
proprietary operating system that runs on almost all Cisco
routers.
I have excellent knowledge on Memory management, kernel
internals, Inter-processor communication (IPC) and device
drivers in Cisco IOS and have been doing sustenance of these
components, which involves debugging internal and customer-
found bugs and adding new featurettes. I was part of the
team working on providing redundant facility for High
Availability Systems.
Have proposed a Garbage collector implementation for
Cisco IOS. And have a good understanding of High Availability
and Check pointing. Have also developed a tool called ISRHOG,
which points out all bad processes that project which aims at
improving voice performance.
Other than this I have Excellent Knowledge in C and C++
Programming and have been certified by Brain bench as Master's
in C with a score of 4.6 (Out of 5.0)
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Tributes
The
CLOOP model was reviewed by Neuralmachine and posted at their site a one
of the best implementations for BPN.
Was
Awarded for Customer Satisfaction in HCL.
To Present "Real time systems - A Pessimistic approach" in the Embedded systems Conference at SFO, April 2003. Here are the presentation slides and here is the proceedings
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Skill
Sets
RTOS and Embedded Systems - have extensively worked on Cisco IOS. And have
designed the implementation of a complete RTOS named PLASTIC for Atheros
Communications. These projects have helped to obtain excellent knowledge
of RTOS internals and implementation details.
Excellent programming skills in C/ C++ Programming in C - Certified as
MASTERS in C by Brain Bench, score 4.6.
Unix Internals and systems programming with C.
Real-time and embedded system architectures and implementations.
Specialization in Real time bounded and dynamic memory management
and Garbage collection.
Excellent skills in MIPS Architecture and assembly programming.
Have worked with the implementation of Backpressure, Redundant Facility,
Check Pointing, and other High Availability infrastructures.
Windows Internals and Kernel Driver Architecture. Video, Network Miniport
and Other Kernel Driver architectures. Use of WinDBG extensively.
Intel X86 architecture and kernel implementation details over it.
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PARTIAL LIST OF PROJECTS
1) IOS Infrastructure Group
Cisco IOS Memory Management, IOS Kernel, IPC Sustenance and enhancements.
Responsibilities: Is a part of a 3-member team in sustaining Inter
Process communication, memory module, and other core Os components
in Cisco IOS.
The Project:
This project involves fixing the customer found bugs as well as
internally found bugs. This includes memory corruption, bus errors,
and memory leak, communication mechanism between processes and
processors, timing and synchronization problems in IPC. Os related
problems.
I have handled CAP and critical bugs related to IPC and OS.
New featurettes were added including
a) Interrupt level Previewing in IPC.
b) Implemented Adaptive Cache Allocation for IPC buffers.
c) Tool to measure and isolate Voice unfriendly applications
in power Pc and MIPS platforms.
Lastly I was working on the redundant facility for High Availability
systems.
Environment: gcc cross compilers for MIPS, ppc and 68k, cscope, gid,
Clearcase and gdb.
Work Location: HCL-Cisco ODC Chennai, India
2) Design Engineer:
Systems / VLSI design/ verification
Responsibilities:
Development of Mips4KP assembly code for bring up and operation of the
core in Simulation and emulation and real boards, including processor
initialization, cache initialization, structured interrupt handling,
icache and dcache production testing and integrating assembly language
infrastructure into digital verification. Digital verification of 802.11a
chipsets.
Current assignment includes developing an NDIS miniport for our wireless
network chip. This project provides a huge insight into windows internals
and driver architectures.
Also have proposed an Assembly testing infrastructure to write DV assembly
tests, saving time and easy to use.
Project:
In this project I had an experience of getting inside out of the MIPS 4KP
core and its initialization, structured interrupt handling, cache
management, management and other system level routines. Have excellent
insight into the MIPS core through an RTOS perspective.
Have developed numerous code for all the above-mentioned
functionalites.
Tools: Sde-GCC compile and SDE_GDB debugger, perforce, vera...
3) PLASTIC - Pretty Little And Solid TIming Constrained RTOS
This project driven by and aims at creating a real time OS. Which
provides,
. Bounded response times for certain classes of processes
. Provides a Pre-emptive, priority driven scheduling for the rest of
the tasks
. Provides structured exception handling.
. Provides Structured Memory management
. Initially to be ported on to the MIPS platform due to my expertise
domain.
. Provides Inter-task communication primitives and scalable timer
implementations.
. Provides support for Networking and general Driver architectures.
. Provides an easily portable interface.
A microkernal based RTOS with minimal configurations to bring up test boards
and run tests on them. Previously tests were run sequentially and the stress
on the bus was not a typical real time example, but after we would complete
this RTOS we would be able to simulate a real time environment by running
simultaneous tests and putting lots of traffic on the system bus.
The platform this is targeted would be a MIPS based SOC solutions.
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